Verilog Parser (Front End)

The Verilog parser (front end) enables the construction of Verilog custom compilers, analysis tools, or source transformation tools. It is a member of SD's family of language front ends, based on first-class infrastructure (DMS) for implementing such custom tools. The Verilog front end includes:

  • Lexical analysis including ASCII and ISO 8859-1
    • Conversion of literal values (numbers, escaped strings) into native values to enable easy computation over literal values
    • String literals represented internally in Unicode to support 16-bit characters
  • Explicit grammar directly implements multiple Verilog standards
    • Full IEEE 1364 2001 Verilog parser
    • Option for IEEE 1364 1995 Verilog dialect
    • Option for SystemVerilog 3.1a dialect
    • Option for (System)Verilog IEEE1800_2012 dialect
  • Preprocessor support
    • Option to parse preserving preprocessor conditional directives, macros and include directives
  • Automatic construction of complete abstract syntax tree
    • Capture of comments and formats (shape) of literal values
    • Capture of ambiguous parses during parsing
    • Ability to parse large systems of files into same workspace, enabling interprocedural and cross-file analysis/transformation
    • Ability to parse different languages into same workspace, enabling codesign analysis/transformation
  • Facilities to process syntax trees
    • Complete procedural API to visit/query/update/construct/print syntax trees
    • Source regeneration by prettyprinting and/or fidelity printing of syntax trees with comments and lexical formats
    • Automatically generated source-to-source transformation system
    • Ability to define custom attribute-grammar-based analyzers
    • Easy to write boolean simplification/processing rules using DMS's AC source-to-source transformations
    • Boolean Decision Diagrams (BDDs) for handling complex boolean symbolic operations quickly and at scale
  • Available as source code to enable complete customization
    • Means to manage multiple language dialects with highly shared common core
  • Robustness due to careful testing and application across many customers

Many of these facilities come as a consistent consequence of the front end being built to top of DMS.

Here are some sample tools (many offered by SD as products) built using the Verilog front end:

SD also offers:

  • VHDL parser (front end)
  • SystemC parser (front end)
  • C++ parser (front end)
  • C parser (front end)

Your organization may use DMS with the Verilog front end to implement and deploy your own custom tools. The sample tools can be obtained in source form as part of the Verilog front end for customization. Semantic Designs is also willing to build custom tools under contract.

For more information:    Follow us at Twitter: @SemanticDesigns

Verilog Parser
Front End